RDCOLLIE=0, RAMRDY=0, ERSAREQ=0, SWAP=0, EEERDY=0, PFLSH=0, CCIE=0, ERSSUSP=0
Flash Configuration Register
| EEERDY | no description available 0 (0): For devices with FlexNVM: FlexRAM is not available for EEPROM operation. 1 (1): For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes to the FlexRAM clear EEERDY and launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup. |
| RAMRDY | RAM Ready 0 (0): For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available. 1 (1): For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available. |
| PFLSH | Flash memory configuration 0 (0): For devices with FlexNVM: Flash memory module configured for FlexMemory that supports data flash and/or EEPROM. For devices with program flash only: Reserved 1 (1): For devices with FlexNVM: Reserved. For devices with program flash only: Flash memory module configured for program flash only, without support for data flash and/or EEPROM |
| SWAP | Swap 0 (0): Physical program flash 0 is located at relative address 0x0000 1 (1): If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH flag is not set, physical program flash 0 is located at relative address 0x0000 |
| ERSSUSP | Erase Suspend 0 (0): No suspend requested 1 (1): Suspend the current Erase Flash Sector command execution. |
| ERSAREQ | Erase All Request 0 (0): No request or request complete 1 (1): Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. |
| RDCOLLIE | Read Collision Error Interrupt Enable 0 (0): Read collision error interrupt disabled 1 (1): Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]). |
| CCIE | Command Complete Interrupt Enable 0 (0): Command complete interrupt disabled 1 (1): Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. |